The present invention relates to flash memories and, more particularly, to a flash memory with memory cells programmed with more than one bit per cell. Particularly, the present invention includes storing in a single page of the memory more than one density (bits/cell).
Flash memory is a type of non-volatile memory. Non-volatile memory stores information on a silicon chip in a way that does not need power to maintain the information in the chip. If power to the chip is turned off, the information is retained without consuming any power. Flash memory is made in different forms including NOR flash and NAND flash. The names refer to the similarity of the interconnections between storage cells in the two types of flash memory to the well-known NOR and NAND logic circuits. A limitation of flash memory is that while flash memory can be read or programmed, for instance in NOR flash a byte or word at a time in a random access fashion, a block of memory must be erased at the same time. A block is the smallest chunk of memory that is erased in one operation. In NAND flash memory, the memory is programmed (i.e. written) in a random access fashion a page at a time. A block is typically much larger than a page in NAND flash.
To overcome this limitation and others, a Flash File System (FFS) was disclosed in U.S. Pat. No. 5,404,485, which is assigned to the assignee of the present application and is hereby incorporated by reference as if fully set forth herein. FFS provides a system of data storage and manipulation on flash devices which allows these devices to emulate magnetic disks. In the existing art, applications or operating systems interact with the flash storage subsystem not using physical addresses but rather virtual addresses. There is an intermediary layer between the software application and the physical device that provides a mapping from the virtual addresses into the physical addresses. The intermediary layer that does the mapping described above may be a software driver running on the same CPU on which the applications run. Alternatively, the intermediary layer may be embedded within a controller that controls the flash device and serves as the interface point for the main CPU of the host computer when the host computer accesses the storage. This is for example the situation in removable memory cards such as secure digital (SD) cards or multimedia cards (MMC), where the card has an on-board controller running a firmware program that among other functions, implements the type of mapping described above.
Software or firmware implementations doing such address mappings are typically called “flash management systems” or “flash file systems”. The latter term is a misnomer, as the implementations do not necessarily support “files”, in the sense that files are used in operating systems or personal computers, but rather support block device interfaces similar to those exported by hard disk software drivers. Still, the term is commonly used, and “flash file system” and “flash management system” are used herein interchangeably.
For NAND-type flash devices, the mapping is done as follows, referring to FIG. 1 (prior art): Physical address space 13 is composed of units 111 that are actually the erase blocks i.e. the smallest chunks that can be erased. The terms “block” and “erase block” are used herein interchangeably. Each physical unit 111 contains one or more physical pages 113, where a “page” is the smallest chunk that can be written. A virtual address space 11 is composed of virtual units 121 that have the same size as the physical units. Each virtual unit contains one or more virtual pages 123, having the same size as physical pages 113. When a virtual address is provided by an application, for reading or writing, the virtual unit number to which that address belongs is extracted from the virtual address. There is a mapping that assigns to each virtual unit 121 either one physical unit 111 or a chain of more than one physical unit 111. Then physical page 113 corresponding to requested virtual page 123 within virtual unit 121 is located within the corresponding physical unit(s) 111, using a “local” mapping rule that relates virtual pages 123 to physical pages 113, or using control information stored with physical pages 113.
Typically, each memory cell within a flash memory stores one bit of information. The traditional way to store a bit in a flash memory cell has been by supporting two states of the cell. One state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell, the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within the floating gate. Typically, one state is with zero charge in the floating gate and is the unwritten state of the cell after being erased (commonly defined to represent the “1” state) and the other state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. It is possible to read the stored bit by checking the threshold voltage of the cell. If the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage. All that is needed is to correctly identify in which of the two states the cell is currently located. For this purpose it is sufficient to compare the threshold voltage of the cell to a reference voltage that is between the two states, and to determine if the cell's threshold voltage is below or above the reference value.
FIG. 1A (prior art) shows graphically how this works. Specifically, FIG. 1A shows a distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due to, for example, small variations in impurity concentrations or defects in the silicon structure), applying the same programming operation to all the cells does not cause all the cells to have exactly the same threshold voltage. Instead, the threshold voltage is distributed as shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the central voltage value of the left peak (labeled 1) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the left peak. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the central voltage of the right peak (labeled 0) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the right peak. In recent years, a new kind of flash device has appeared on the market, using “Multi Level Cells” (MLC). The term “Multi-Level Cell” is misleading because flash memory with a single bit per cell uses multiple i.e. two levels, as described above. Therefore, the term “Single Bit Cell” (SBC) is used hereinafter to refer to a memory cell of two levels and the term “Multi-Bit Cell” (MBC) is used hereinafter to refer to a memory cell of more than two levels, i.e. more than one bit per cell. A representative prior art example of an MBC flash device is found in U.S. Pat. No. 5,434,825 disclosed by Harari. The present discussion is directed primarily to an MBC flash memory with two bits per cell. It should however be understood that the present invention is equally applicable to flash memory devices that support more than two bits per cell.
A single MBC cell storing two bits of information is in one of four different states. As the cell's “state” is represented by the cell's threshold voltage, an MBC cell supports four different valid ranges for the cell's threshold voltage. FIG. 1B (prior art) shows the threshold voltage distribution for a typical MBC cell of two bits per cell. As expected, FIG. 1B has four peaks, each peak corresponding to one state. As for the SBC, each state is actually a voltage range and not a single voltage. When reading the cell's contents, the cell's threshold voltage must be correctly identified in a definite voltage range.
In most MBC devices the device manufacturer does not give the user any means to select the number of bits per cell in a given block, i.e the number of bits per cell is the same for all the cells in the device. However, in some MBC devices the number of bits per cell can be reduced on parts of a device in order to achieve higher performance or higher reliability during programming. For example, a MBC flash may store two bits per cell in most of its blocks, but under software program control, store only one bit per cell in other blocks. MBC flash devices having different blocks within the same device storing different numbers of bits per cell have been disclosed in prior art. Representative prior art includes Lee et al. U.S. Pat. No. 5,930,167, Gonzales et al. U.S. Pat. No. 6,807,106, and Chen U.S. Pat. Nos. 6,456,528 and 6,717,847. Chen discloses switching blocks to a lower number of bits per cell when the blocks approach the end of their expected useful lifetime.
In MBC devices, the different peaks of the threshold voltage distribution graph are used for encoding the values of the bits stored in the cell. We shall use the notation and terminology of Lasser U.S. Patent Application 60/553,798 entitled “States encoding in multi-level cell flash memory” (“Lasser '798”), incorporated by reference for all purposes as if fully set forth herein. Referring to FIG. 1B, showing the threshold voltage distributions of an MBC cell. The graph's peaks are labeled (from left to right) “11”, “10”, “00”, “01”. This means that
When a cell is in state A, (the first state from the left), it represents a “1” for the lower bit and a “1” for the upper bit, (this is the initial un-programmed state of the cell)
When a cell is in state B (the second state from the left), it represents a “0” for the lower bit and a “1” for the upper bit.
When a cell is in state C (the third state from the left), it represents a “0” for the lower bit and a “0” for the upper bit.
When a cell is in state D (the fourth state from the left), it represents a “1” for the lower bit and a “0” for the upper bit.
The encoding scheme presented above for a two-bit-per-cell MBC is the one proposed by Chen in U.S. Pat. No. 6,522,580. A different scheme is proposed by Tanaka U.S. Pat. No. 6,643,188, where the order of the bit assignments (from left to right along the threshold voltage axis) is: “11”, “10”, “01”, “00”. The interpretation of this scheme is:
When a cell is in state A (the first state from the left), it represents a “1” for the lower bit and a “1” for the upper bit, (this is the initial un-programmed state of the cell).
When a cell is in the state B (second state from the left), it represents a “0” for the lower bit and a “1” for the upper bit.
When a cell is in state C (the third state from the left), it represents a “1” for the lower bit and a “0” for the upper bit.
When a cell is in state D (the fourth state from the left), it represents a “0” for the lower bit and a “0” for the upper bit.
A cell designed for MBC operation e.g. in four states is typically operable as an SBC cell with two states. For example, Conley et al. in U.S. Pat. No. 6,426,893 incorporated by reference for all purposes as if fully set forth herein, disclosed using both MBC and SBC modes within the same device, selecting certain parts of the device to operate with highest density in MBC mode, while other parts are used in SBC mode to provide better performance.
MBC devices provide a significant cost advantage. An MBC device with two bits per cell requires about half the area of a silicon wafer than an SBC of similar capacity. However, there are drawbacks to using MBC flash. Average read and write times of MBC memories are longer than of SBC memories, resulting in worse performance. Also, the reliability of MBC is lower than SBC. The difference between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leakage of stored charge causing a threshold voltage drift or interference from operating neighboring cells) that are insignificant in SBC because of the large gap between the two states, may cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower performance specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles.
Let us now consider the way flash management software works. The following explanation is for NAND-type flash devices, but this is not meant to limit the invention in any way. The host processor to which the flash storage system is attached interacts with it by reading and writing data sectors (also called “user data” herein), typically the size of 512 bytes. On the physical flash devices each sector is stored in page 113 (typically also 512 bytes, but there are also devices with other page sizes), which is the minimal chunk of data for writing operations. A sector often refers to the data stored in page 113. The term “sector” and the term “page” are used herein interchangeably.
For correct and efficient operation the flash management software must keep certain control information for each and every sector. For example, a sector can be accompanied by flags indicating whether it currently contains valid data, whether it is free to be used (without having to be erased before that), etc. Additionally, there is a need to keep information identifying the address mapping associated with a sector, for example where is this sector located in the logical or virtual address space by which the host interacts with the storage system. Some control information may be associated not with a single sector but with the whole group of sectors stored in the same block (a block is the minimal chunk of data for erase operations). An example for this is the storage of “erase marks” indicating that the block containing them had completed a valid erase operation and may be reliably used for writing data, as taught by Lasser et al. U.S. patent application Ser. No. 10/298,094 entitled “Detecting partially erased units in flash devices”. This type of block-related information is typically kept in the first sector of the block, accompanying the data stored in that sector. Flash management systems operating according to these principles are very well known in the art. See for example Lasser U.S. Pat. No. 6,678,785 entitled “Flash management system using only sequential write”, and Ban U.S. Pat. No. 5,937,425 entitled “Flash file system optimized for page-mode flash technologies”, which patents are incorporated by reference for all purposes as if fully set forth herein. Because of the common need to store additional information associated with a data sector, NAND flash devices are built with an additional amount of storage space associated with each sector (called “extra area” or “spare area”), providing the flash management software with room to store control information. Typically such devices provide 16 bytes of extra area per each 512 bytes of regular storage space.
The control information described above is used by the flash management software as input for management algorithms. Therefore, the control information is critical to the correct operation of the flash system. While an error in the user data does not damage the flash management system, an error in the control information might result in the loss of a whole sector, a whole block, or (in extreme cases) even the whole disk contents. Hence, there is great importance in being able to read the control information with the highest reliability.
Also because the control information described above is used by the flash management software as input for its management algorithms, control information is accessed quite frequently, on the average more frequently than the associated user data. For example, when mounting the flash storage device (that is—when initializing the flash management software after system power up), the control information of many sectors must be read in order to construct and initialize the address translation tables of the software, even though no user data is actually read at that time. Also during normal operation, there are many cases where in order to locate a data sector requested by the host, we must read the control information of quite a few sectors in order to locate the requested one. Therefore there is great performance advantage in being able to read the control information (without the user data in the associated sector) as fast as possible.
In all prior art flash systems using the above methods the control information is stored using the same writing modes as the regular user data. If the flash device uses MBC mode, then both user data and control information are stored in MBC mode. And if the flash device uses SBC mode, then both user data and control information are stored in SBC mode. So both user data and control information have the same reliability and the same reading speed.
Prior art flash memory systems do not support separating “modes” between user data and control information. Control information is stored in the same page as the related user data and in many cases the control information is being stored together with the user data in the same write operation. Prior art flash devices do not support a single writing operation which writes some memory cells using MBC mode and other memory cells using SBC mode, because much of the internal circuitry of the flash device which carries out the writing operation is shared between all the cells being written together, and the prior art circuitry cannot act at the same time in two different modes. Secondly, the flash device must be instructed (by the controller of the flash system) in which mode, MBC or SBC, the page is programmed, and the current interfaces of existing flash devices do not support mixing modes within the same basic operation.
Thus there is a need and it would be advantageous to have a method for storing control information into the flash device in the same pages with the same writing operations as the user data related to the control information.